Transfer a pulse from fast clock to slow clock

A lot of time during digital design interviews a simple looking question is asked to transfer a pulse from fast clock domain to slow clock domain. At first you think that all you need to do is to extend this pulse such that it can be sampled by receiver’s clock, but it is not that simple. We have to take a step further. There are few problems here:

1. The obvious problem is that the 2 clocks are asynchronous to each other and we will need double synchronizers to resolve metastability.
2. Even when we know the relationship between fast and slow clock, we do not know for how long the pulse should be extended because of clock skews.

Quickly moving to solution space. To safely transmit this pulse, using a flop (clocked by fast clock) we can extend the pulse and we will continue to extend it till we detect the active edge of slow clock. We can come up with this truth table using this concept:

Pulse	Qout (fast clock)	Edge Detection (slow clock)	Next (fast clock)
0	0	0	0
0	0	1	0
0	1	0	1
0	1	1	0
1	0	0	1
1	0	1	1
1	1	0	1
1	1	1	1

Resolving Kmap for this table, D-input logic (or next logic) will be:

D = Pulse + Qout . ~Edge_detection

The above circuit will act a base idea for our actual design. Let's first look at how we can design edge design logic for slow clock domain receiver. We should synchronize slow clock with fast clock using standard double sync flops as show below. Note that we have a follower flop immediately after double sync flops. Ideally, we could have made the 2nd flop in double sync arrangements, but generally in most RTL libraries double sync flops comes as a package.

 Looking at the waveform, it should be clear how above edge detection circuit is working.

Finally joining all the pieces together. Note that we still have to synchronize pulse extension from fast clock to slow clock.

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